This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-330623, filed Oct. 30, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, particularly, to an electrically rewritable nonvolatile semiconductor memory device consisting of cell units such as a NAND cell, a NOR cell, a DINOR cell (Divided NOR cell) and an AND cell.
2. Description of the Related Art
The conventional semiconductor memory device includes an electrically rewritable EEPROM (Electrically Erasable Programmable Read Only Memory). Particularly, a NAND type EEPROM having a block construction consisting of NAND cells having a plurality of memory cells connected in series attracts attentions because it is possible to increase the degree of integration.
The memory cell of the NAND type EEPROM is formed of MOSFET""s having a stacked gate structure including a floating gate acting as a charge storage layer and a control gate, which are stacked one upon the other on a semiconductor substrate with a gate insulating film interposed therebetween. The NAND cell is formed of adjacent memory cells connected in series with the source and drain used commonly.
In the NAND type EEPROM, these plural NAND cells are connected to a bit line with each NAND cell forming a unit and are arranged to form a matrix, thereby constructing a memory cell array. The memory cell array is formed in high density in a p-well on a semiconductor substrate or on a p-type semiconductor substrate.
The drains on one terminal section of the NAND cells arranged in the column direction of the memory cell array are connected to a common bit line through select transistors, and the other terminal section of the NAND cells are similarly connected to a common source line through select transistors. The control gate of the memory cell and the select gate of the select transistor are formed as a series of control gate lines (word lines) and select gate lines in the row direction of the memory cell array.
The conventional NAND type EEPROM is operated as follows.
Specifically, the data program operation is successively performed starting with the memory cell positioned remotest from the bit line contact of the NAND cell. The memory cell for programming the data is selected, and a high voltage Vpp (about 20V) for the data programming is applied to the control gate line to which is connected the selected memory cell. Also, an intermediate potential Vmw (about 10V) is applied to the control gate line of the memory cell positioned closer to the bit line than the selected memory cell and to the select gate line of the select transistor. Further, 0V or an intermediate potential Vmb (about 8V) is applied to the bit line of the selected memory cell in accordance with the level of the data.
If 0V is applied to the bit line, 0V is transmitted to the drain of the memory cell so as to bring about an electron injection from the drain into the floating gate, with the result that the threshold voltage of the selected memory cell is shifted in the positive direction. This is the xe2x80x9c1xe2x80x9d programmed state. Also, if the intermediate potential Vmb is imparted to the bit line, the electron injection into the floating gate does not take place, with the result that the threshold voltage of the selected memory cell is not changed so as to remain in the negative value. This is the xe2x80x9c0xe2x80x9d programmed state.
The data erase operation is performed simultaneously in respect of all the memory cells within the block consisting of the selected NAND cells. All the control gate lines within the selected block are set at 0V, and voltage of about 20V is applied as Vpp to the p-well (or p-type substrate) so as to put the bit line, the source line, the control gate line and the select gate line in the unselected block in the floating state. In this fashion, the electrons in the floating gates included in all the memory cells within the selected block are discharged into the p-well (or a p-type substrate) so as to shift the threshold voltage of the memory cell in the negative direction.
The data read operation is performed by detecting whether or not an electric current flows from the bit line into the source line through the selected memory cell and a plurality of unselected memory cell, with the unselected control gate line in the selected block set at Vread, with the selected control gate line set at 0V, and with the select gate line also set at Vread.
As described above, in the NAND type EEPROM, each of the unselected control gate line and the select gate line in the selected block is set at Vread during the data read operation. In this case, a serious problem is generated as described below.
In order to increase the reading speed, it is necessary to increase the current flowing through the NAND cell including the selected memory cell having the xe2x80x9c0xe2x80x9d data programmed therein. For example, where a single NAND cell is formed of 8 memory cells, it is possible to increase the current flowing through the NAND cell by lowering the resistance of the unselected 7 memory cells.
In order to lower the resistance of the unselected 7 memory cells, it is highly effective to enhance the level of Vread applied to the control gates of these 7 memory cells during the read operation. In this case, Vread is also applied simultaneously to the select gate of the select transistor.
The memory cell includes two insulating films formed between the control gate and the channel of the memory cell, i.e., an insulating film formed between the control gate and the floating gate, and another insulating film formed between the floating gate and the channel. It follows that, even if the level of Vread is enhanced, the intensity of the electric field applied to the insulating film positioned between the floating gate and the channel is lowered.
In the select transistor, however, the select gate of the select transistor and the floating gate of the memory cell are formed of the same wiring layer and, thus, only one insulating film is formed between the select gate of the select transistor and the channel. It follows that the intensity of the electric field applied to the insulating film is increased, with the result that breakdown of the insulating film tends to be brought about.
The present invention provides a nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device according to an embodiment of the present invention, the voltage of the control gate of the memory cell included in the block selected in the data read operation is made different from the voltage of the select gate of the select transistor included in the selected block so as to make it possible to read out at a high speed the program data in the memory cell without bringing about breakdown of the insulating film formed between the select gate of the select transistor and the channel. Similarly, a high speed reading can be made possible in respect of a DINOR cell, an AND cell, a NOR cell and a NAND cell having a single memory cell connected thereto.
According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a memory cell array including memory cell units each comprising at least one select transistor and at least one memory cell and arranged to form an array; a control gate line including control gates of memory cells connected continuously in a row direction of the memory cell array; and a select gate line including select gates of select transistors connected continuously in the row direction of the memory cell array; wherein the highest value of a first voltage level of the control gate line in a selected memory cell unit differs from a second voltage level of all the select gate lines of the memory cell unit during a read operation of a program data programmed in the memory cell and during a verify read operation of the program data.
According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a memory cell array including memory cell units each comprising first and second select transistors and at least one memory cell and arranged to form an array; a control gate line including control gates of memory cells connected continuously in a row direction of the memory cell array; a first select gate line including select gates of the first select transistors connected continuously in the row direction of the memory cell array, and a second select gate line including select gates of the second select transistors connected continuously in the row direction of the memory cell array; wherein a first voltage level of the first select gate line in the selected memory cell unit differs from a second voltage level of the second select gate line in the memory cell units during a read operation of a program data programmed in the memory cell and during a verify read operation of the program data.